diff --git a/ddr3_general_design.srcs/sources_1/ip/ddr3_data_fifo/ddr3_data_fifo.xci b/ddr3_general_design.srcs/sources_1/ip/fifo_rd_data/fifo_rd_data.xci similarity index 99% rename from ddr3_general_design.srcs/sources_1/ip/ddr3_data_fifo/ddr3_data_fifo.xci rename to ddr3_general_design.srcs/sources_1/ip/fifo_rd_data/fifo_rd_data.xci index 0abad8f..aa87f58 100644 --- a/ddr3_general_design.srcs/sources_1/ip/ddr3_data_fifo/ddr3_data_fifo.xci +++ b/ddr3_general_design.srcs/sources_1/ip/fifo_rd_data/fifo_rd_data.xci @@ -6,7 +6,7 @@ 1.0 - ddr3_data_fifo + fifo_rd_data @@ -217,7 +217,7 @@ 0 0 0 - 0 + 1 0 0 0 @@ -337,7 +337,7 @@ 0 Slave_Interface_Clock_Enable Common_Clock - ddr3_data_fifo + fifo_rd_data 64 false 6 @@ -473,7 +473,7 @@ false false false - false + true Active_High 0 false @@ -556,9 +556,9 @@ - + diff --git a/ddr3_general_design.srcs/sources_1/ip/fifo_rd_info/fifo_rd_info.xci b/ddr3_general_design.srcs/sources_1/ip/fifo_rd_info/fifo_rd_info.xci new file mode 100644 index 0000000..c858dd8 --- /dev/null +++ b/ddr3_general_design.srcs/sources_1/ip/fifo_rd_info/fifo_rd_info.xci @@ -0,0 +1,568 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_rd_info + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 1 + 0 + 6 + BlankString + 6 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 6 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + virtex7 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 2 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 512x36 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 62 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 61 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 6 + 64 + 1 + 6 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 6 + 64 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 6 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_rd_info + 64 + false + 6 + false + false + 0 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + 0 + 62 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 61 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 6 + 64 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 6 + 64 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 6 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Synchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + false + false + false + true + Active_High + 0 + false + Active_High + 1 + false + 6 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + virtex7 + + + xc7vx690t + ffg1761 + VERILOG + + MIXED + -2 + + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2018.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ddr3_general_design.srcs/sources_1/ip/ddr3_info_fifo/ddr3_info_fifo.xci b/ddr3_general_design.srcs/sources_1/ip/fifo_rw_addr/fifo_rw_addr.xci similarity index 99% rename from ddr3_general_design.srcs/sources_1/ip/ddr3_info_fifo/ddr3_info_fifo.xci rename to ddr3_general_design.srcs/sources_1/ip/fifo_rw_addr/fifo_rw_addr.xci index ea6cfa1..b2c078a 100644 --- a/ddr3_general_design.srcs/sources_1/ip/ddr3_info_fifo/ddr3_info_fifo.xci +++ b/ddr3_general_design.srcs/sources_1/ip/fifo_rw_addr/fifo_rw_addr.xci @@ -6,7 +6,7 @@ 1.0 - ddr3_info_fifo + fifo_rw_addr @@ -154,7 +154,7 @@ 0 6 BlankString - 35 + 29 1 32 64 @@ -162,7 +162,7 @@ 64 2 0 - 35 + 29 0 1 0 @@ -217,7 +217,7 @@ 0 0 0 - 0 + 1 0 0 0 @@ -337,7 +337,7 @@ 0 Slave_Interface_Clock_Enable Common_Clock - ddr3_info_fifo + fifo_rw_addr 64 false 6 @@ -413,7 +413,7 @@ false false false - 35 + 29 64 1024 16 @@ -422,7 +422,7 @@ 1024 16 false - 35 + 29 64 Embedded_Reg false @@ -473,7 +473,7 @@ false false false - false + true Active_High 0 false @@ -556,9 +556,9 @@ - + diff --git a/ddr3_general_design.srcs/sources_1/ip/ddr3_cmd_fifo/ddr3_cmd_fifo.xci b/ddr3_general_design.srcs/sources_1/ip/fifo_rw_cmd/fifo_rw_cmd.xci similarity index 99% rename from ddr3_general_design.srcs/sources_1/ip/ddr3_cmd_fifo/ddr3_cmd_fifo.xci rename to ddr3_general_design.srcs/sources_1/ip/fifo_rw_cmd/fifo_rw_cmd.xci index fbe7517..243b545 100644 --- a/ddr3_general_design.srcs/sources_1/ip/ddr3_cmd_fifo/ddr3_cmd_fifo.xci +++ b/ddr3_general_design.srcs/sources_1/ip/fifo_rw_cmd/fifo_rw_cmd.xci @@ -6,7 +6,7 @@ 1.0 - ddr3_cmd_fifo + fifo_rw_cmd @@ -337,7 +337,7 @@ 0 Slave_Interface_Clock_Enable Common_Clock - ddr3_cmd_fifo + fifo_rw_cmd 64 false 6 @@ -556,7 +556,6 @@ - diff --git a/ddr3_general_design.srcs/sources_1/ip/fifo_wr_mask_data/fifo_wr_mask_data.xci b/ddr3_general_design.srcs/sources_1/ip/fifo_wr_mask_data/fifo_wr_mask_data.xci new file mode 100644 index 0000000..e3b1442 --- /dev/null +++ b/ddr3_general_design.srcs/sources_1/ip/fifo_wr_mask_data/fifo_wr_mask_data.xci @@ -0,0 +1,564 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_wr_mask_data + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 1 + 0 + 6 + BlankString + 576 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 576 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + virtex7 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 512x72 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 62 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 61 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 6 + 64 + 1 + 6 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 6 + 64 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 6 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_wr_mask_data + 64 + false + 6 + false + false + 0 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + 0 + 62 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 61 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 576 + 64 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 576 + 64 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 6 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Synchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 6 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + virtex7 + + + xc7vx690t + ffg1761 + VERILOG + + MIXED + -2 + + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2018.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_ctrl_module.v b/ddr3_general_design.srcs/sources_1/new/ddr3_ctrl_module.v deleted file mode 100644 index ad9cc3c..0000000 --- a/ddr3_general_design.srcs/sources_1/new/ddr3_ctrl_module.v +++ /dev/null @@ -1,168 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2025/01/06 15:49:11 -// Design Name: -// Module Name: ddr3_ctrl_module -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module ddr3_ctrl_module( - // Clock and reset signals - input sys_clk_i, - input sys_rst_i, - input ui_clk_i, - input ui_rst_i, - - // Read & Write interface signals - input [ 1:0] rw_req_i, - output rw_ack_o, - output rw_full_o, - output rd_valid_o, - output rd_empty_o, - - // User interface signals - output [ 28:0] app_addr_o, - output [ 2:0] app_cmd_o, - output app_en_o, - output [511:0] app_wdf_data_o, - output app_wdf_end_o, - output [ 63:0] app_wdf_mask_o, - output app_wdf_wren_o, - input [511:0] app_rd_data_i, - input app_rd_data_end_i, - input app_rd_data_valid_i, - input app_rdy_i, - input app_wdf_rdy_i - ); - - wire wr_req_i; - wire rd_req_i; - - wire [ 2:0] cmd_fifo_din; - wire cmd_fifo_we; - wire cmd_fifo_full; - wire [ 2:0] cmd_fifo_dout; - wire cmd_fifo_re; - wire cmd_fifo_empty; - - wire [ 28:0] addr_i_fifo_din; - wire addr_i_fifo_we; - wire addr_i_fifo_full; - wire [ 28:0] addr_i_fifo_dout; - wire addr_i_fifo_re; - wire addr_i_fifo_empty; - - wire [511:0] wdata_fifo_din; - wire wdata_fifo_we; - wire wdata_fifo_full; - wire [511:0] wdata_fifo_dout; - wire wdata_fifo_re; - wire wdata_fifo_empty; - - // Instantiate the module - ddr3_wr_ctrl ddr3_wr_ctrl_inst( - .sys_clk_i (sys_clk_i), - .sys_rst_i (sys_rst_i), - .ui_clk_i (ui_clk_i), - .ui_rst_i (ui_rst_i), - - .rw_req_i (rw_req_i), - .rw_full_o (rw_full_o), - - .cmd_fifo_full_i (cmd_fifo_full), - .addr_i_fifo_full_i (addr_i_fifo_full), - .wdata_fif_full_i (wdata_fifo_full), - .cmd_fifo_empty_i (cmd_fifo_empty), - .addr_i_fifo_empty_i (addr_i_fifo_empty), - .wdata_fifo_empty_i (wdata_fifo_empty), - - .cmd_fifo_we_o (cmd_fifo_we), - .cmd_fifo_re_o (cmd_fifo_re), - .addr_i_fifo_we_o (addr_i_fifo_we), - .addr_i_fifo_re_o (addr_i_fifo_re), - .wdata_fifo_we_o (wdata_fifo_we), - .wdata_fifo_re_o (wdata_fifo_re) - ); - - // Instantiate the module - ddr3_cmd_fifo ddr3_cmd_fifo_inst ( - .wr_clk (sys_clk_i), - .rd_clk (ui_clk_i), - .rst (sys_rst_i), - .din (cmd_fifo_din), - .wr_en (cmd_fifo_we), - .full (cmd_fifo_full), - .dout (cmd_fifo_dout), - .rd_en (cmd_fifo_re), - .empty (cmd_fifo_empty) - ); - - // Instantiate the module - ddr3_info_fifo ddr3_info_i_fifo_inst ( - .wr_clk (sys_clk_i), - .rd_clk (ui_clk_i), - .rst (sys_rst_i), - .din (addr_i_fifo_din), - .wr_en (addr_i_fifo_we), - .full (addr_i_fifo_full), - .dout (addr_i_fifo_dout), - .rd_en (addr_i_fifo_re), - .empty (addr_i_fifo_empty) - ); - - // Instantiate the module - ddr3_data_fifo ddr3_wdata_fifo_inst ( - .wr_clk (sys_clk_i), - .rd_clk (ui_clk_i), - .rst (sys_rst_i), - .din (wdata_fifo_din), - .wr_en (wdata_fifo_we), - .full (wdata_fifo_full), - .dout (wdata_fifo_dout), - .rd_en (wdata_fifo_re), - .empty (wdata_fifo_empty) - ); - - // Instantiate the module - ddr3_rd_ctrl ddr3_rd_ctrl_inst(); - - // Instantiate the module - ddr3_info_fifo ddr3_info_o_fifo_inst ( - .wr_clk (ui_clk_i), - .rd_clk (sys_clk_i), - .rst (ui_rst_i), - .din (), - .wr_en (), - .full (), - .dout (), - .rd_en (), - .empty () - ); - - // Instantiate the module - ddr3_data_fifo ddr3_rdata_fifo_inst ( - .wr_clk (ui_clk_i), - .rd_clk (sys_clk_i), - .rst (ui_rst_i), - .din (), - .wr_en (), - .full (), - .dout (), - .rd_en (), - .empty () - ); -endmodule diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_rd_fifo_rd_fsm.v b/ddr3_general_design.srcs/sources_1/new/ddr3_rd_fifo_rd_fsm.v deleted file mode 100644 index 00ea43f..0000000 --- a/ddr3_general_design.srcs/sources_1/new/ddr3_rd_fifo_rd_fsm.v +++ /dev/null @@ -1,26 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2025/01/06 16:58:22 -// Design Name: -// Module Name: ddr3_rd_fifo_rd_fsm -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module ddr3_rd_fifo_rd_fsm( - - ); -endmodule diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_rd_fifo_wr_fsm.v b/ddr3_general_design.srcs/sources_1/new/ddr3_rd_fifo_wr_fsm.v deleted file mode 100644 index 17b8e57..0000000 --- a/ddr3_general_design.srcs/sources_1/new/ddr3_rd_fifo_wr_fsm.v +++ /dev/null @@ -1,26 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2025/01/06 16:58:22 -// Design Name: -// Module Name: ddr3_rd_fifo_wr_fsm -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module ddr3_rd_fifo_wr_fsm( - - ); -endmodule diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_rw_in_ctrl.v b/ddr3_general_design.srcs/sources_1/new/ddr3_rw_in_ctrl.v new file mode 100644 index 0000000..3dd3d15 --- /dev/null +++ b/ddr3_general_design.srcs/sources_1/new/ddr3_rw_in_ctrl.v @@ -0,0 +1,119 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/01/13 19:28:48 +// Design Name: +// Module Name: ddr3_rw_in_ctrl +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ddr3_rw_in_ctrl( + input ui_clk_i, + input ui_rst_i, + + input app_rdy_i, + + input fifo_rw_in_empty_i, + output fifo_rw_in_re_o, + output app_en_1d_o + ); + + localparam [2:0] + S_IDLE = 3'b001, + S_WAIT = 3'b100, + S_ACC = 3'b100; + + reg [2:0] c_state; + reg [2:0] n_state; + + reg fifo_rw_in_re; + reg fifo_rw_in_re_1d; + reg app_en; + + assign fifo_rw_in_re_o = fifo_rw_in_re; + assign app_en_1d_o = app_en; + + always @(posedge ui_clk_i or negedge ui_rst_i) begin + if(ui_rst_i) begin + c_state <= S_IDLE; + end else begin + c_state <= n_state; + end + end + + always @(*) begin + fifo_rw_in_re = 1'b0; + app_en = 1'b0; + n_state = S_IDLE; + case(c_state) + S_IDLE: begin + if(!fifo_rw_in_empty_i) begin + fifo_rw_in_re = 1'b1; + n_state = S_WAIT; + end + else begin + n_state = S_IDLE; + end + end + S_WAIT: begin + if(!fifo_rw_in_empty_i) begin + fifo_rw_in_re = 1'b1; + end + n_state = S_ACC; + end + S_ACC: begin + if(app_rdy_i) begin + app_en = 1'b1; + end + + casex({app_rdy_i, !fifo_rw_in_empty_i, fifo_rw_in_re_1d}) + 3'b0xx: begin + n_state = S_ACC; + end + 3'b100: begin + n_state = S_IDLE; + end + 3'b101: begin + n_state = S_ACC; + end + 3'b110: begin + fifo_rw_in_re = 1'b1; + n_state = S_WAIT; + end + 3'b111: begin + fifo_rw_in_re = 1'b1; + n_state = S_ACC; + end + default: begin + n_state = S_IDLE; + end + endcase + end + default: begin + n_state = S_IDLE; + end + endcase + end + + always @(posedge ui_clk_i or negedge ui_rst_i) begin + if(ui_rst_i) begin + fifo_rw_in_re_1d <= 1'b0; + end else begin + fifo_rw_in_re_1d <= fifo_rw_in_re; + end + end + +endmodule diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_rw_module.v b/ddr3_general_design.srcs/sources_1/new/ddr3_rw_module.v new file mode 100644 index 0000000..c7404cb --- /dev/null +++ b/ddr3_general_design.srcs/sources_1/new/ddr3_rw_module.v @@ -0,0 +1,279 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/01/13 18:26:30 +// Design Name: +// Module Name: ddr3_rw_module +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ddr3_rw_module( + // Clock and reset signals + input sys_clk_i, + input sys_rst_i, + input ui_clk_i, + input ui_rst_i, + + // Read & Write interface signals + input ddr3_rw_en_i, + input [ 2:0] ddr3_rw_cmd_i, + input [ 28:0] ddr3_rw_addr_i, + input [ 63:0] ddr3_wr_mask_i, + input [511:0] ddr3_wr_data_i, + input [ 34:0] ddr3_rd_info_i, + input ddr3_rd_rdy_i, + + output ddr3_rw_full_o, + output [ 28:0] ddr3_rd_addr_o, + output [511:0] ddr3_rd_data_o, + output [ 5:0] ddr3_rd_info_o, + output ddr3_rd_valid_o, + output ddr3_rd_full_o, + output ddr3_rd_empty_o, + + // User interface signals + output [ 28:0] app_addr_o, + output [ 2:0] app_cmd_o, + output app_en_o, + output [511:0] app_wdf_data_o, + output app_wdf_end_o, + output [ 63:0] app_wdf_mask_o, + output app_wdf_wren_o, + input [511:0] app_rd_data_i, + input app_rd_data_end_i, + input app_rd_data_valid_i, + input app_rdy_i, + input app_wdf_rdy_i + ); + + reg fifo_rw_in_re_1d; + reg [ 2:0] fifo_rw_cmd_dout_1d; + reg [ 28:0] fifo_rw_addr_dout_1d; + reg fifo_rw_out_re; + + wire fifo_rw_in_re; + wire app_en_1d; + wire app_rdy; + wire fifo_rw_in_empty; + + wire [ 2:0] fifo_rw_cmd_din; + wire fifo_rw_cmd_we; + wire fifo_rw_cmd_full; + wire [ 2:0] fifo_rw_cmd_dout; + wire fifo_rw_cmd_re; + wire fifo_rw_cmd_empty; + + wire [ 28:0] fifo_rw_addr_in_din; + wire fifo_rw_addr_in_we; + wire fifo_rw_addr_in_full; + wire [ 28:0] fifo_rw_addr_in_dout; + wire fifo_rw_addr_in_re; + wire fifo_rw_addr_in_empty; + + wire [575:0] fifo_wr_mask_data_din; + wire fifo_wr_mask_data_we; + wire fifo_wr_mask_data_full; + wire [575:0] fifo_wr_mask_data_dout; + wire fifo_wr_mask_data_re; + wire fifo_wr_mask_data_empty; + + wire fifo_rw_out_empty; + //wire fifo_rw_out_re; + wire fifo_rw_out_valid; + + wire [511:0] fifo_rd_data_din; + wire fifo_rd_data_we; + wire fifo_rd_data_full; + wire [511:0] fifo_rd_data_dout; + wire fifo_rd_data_re; + wire fifo_rd_data_empty; + wire fifo_rd_data_valid; + + wire [ 28:0] fifo_rw_addr_out_din; + wire fifo_rw_addr_out_we; + wire fifo_rw_addr_out_full; + wire [ 28:0] fifo_rw_addr_out_dout; + wire fifo_rw_addr_out_re; + wire fifo_rw_addr_out_empty; + wire fifo_rw_addr_out_valid; + + wire [ 5:0] fifo_rd_info_din; + wire fifo_rd_info_we; + wire fifo_rd_info_full; + wire [ 5:0] fifo_rd_info_dout; + wire fifo_rd_info_re; + wire fifo_rd_info_empty; + wire fifo_rd_info_valid; + + assign ddr3_rw_full_o = fifo_rw_cmd_full || fifo_rw_addr_in_full || fifo_wr_mask_data_full || fifo_rd_info_full; + assign ddr3_rd_addr_o = fifo_rw_addr_out_dout; + assign ddr3_rd_data_o = fifo_rd_data_dout; + assign ddr3_rd_info_o = fifo_rd_info_dout; + assign ddr3_rd_valid_o = fifo_rd_data_valid; + assign ddr3_rd_full_o = fifo_rd_data_full || fifo_rw_addr_out_full || fifo_rd_info_full; + assign ddr3_rd_empty_o = fifo_rd_data_empty && fifo_rd_info_empty && fifo_rw_addr_out_empty; + + assign app_addr_o = fifo_rw_addr_dout_1d; + assign app_cmd_o = fifo_rw_cmd_dout_1d; + assign app_en_o = app_en_1d; + assign app_wdf_data_o = fifo_wr_mask_data_dout[511:0]; + assign app_wdf_end_o = app_en_1d && (fifo_rw_cmd_dout_1d == 3'b000); + assign app_wdf_mask_o = fifo_wr_mask_data_dout[575:511]; + assign app_wdf_wren_o = app_en_1d && (fifo_rw_cmd_dout_1d == 3'b000); + assign fifo_rd_out_valid_o = fifo_rd_data_valid && fifo_rw_addr_out_valid && fifo_rd_info_valid ; + + assign fifo_rw_cmd_we = ddr3_rw_en_i; + assign fifo_rw_cmd_din = ddr3_rw_cmd_i; + assign fifo_rw_addr_in_we = ddr3_rw_en_i; + assign fifo_rw_addr_in_din = ddr3_rw_addr_i; + assign fifo_wr_mask_data_we = ddr3_rw_en_i && (ddr3_rw_cmd_i == 3'b000); + assign fifo_wr_mask_data_din = {ddr3_wr_mask_i, ddr3_wr_data_i}; + assign fifo_rd_info_we = ddr3_rw_en_i && (ddr3_rw_cmd_i == 3'b001); + assign fifo_rd_info_din = ddr3_rd_info_i; + + assign app_rdy = app_rdy_i && app_wdf_rdy_i; + assign fifo_rw_in_empty = fifo_rw_cmd_empty && fifo_rw_addr_in_empty; + assign fifo_rw_cmd_re = fifo_rw_in_re; + assign fifo_rw_addr_in_re = fifo_rw_in_re; + assign fifo_wr_mask_data_re = fifo_rw_in_re_1d && (fifo_rw_cmd_dout == 3'b000); + + assign fifo_rd_data_we = app_rd_data_valid_i; + assign fifo_rd_data_din = app_rd_data_i; + + assign fifo_rd_data_re = fifo_rw_out_re; + assign fifo_rd_info_re = fifo_rw_out_re; + + always @(posedge ui_clk_i or negedge ui_rst_i) begin + if(ui_rst_i) begin + fifo_rw_in_re_1d <= 1'b0; + end else begin + fifo_rw_in_re_1d <= fifo_rw_in_re; + end + end + + always @(posedge ui_clk_i or negedge ui_rst_i) begin + if(ui_rst_i) begin + fifo_rw_cmd_dout_1d <= 3'b000; + fifo_rw_addr_dout_1d <= 29'b0; + end + else begin + if(fifo_rw_in_re_1d) begin + fifo_rw_cmd_dout_1d <= fifo_rw_cmd_dout; + end + else begin + fifo_rw_cmd_dout_1d <= fifo_rw_cmd_dout_1d; + end + + if(fifo_rw_in_re_1d) begin + fifo_rw_addr_dout_1d <= fifo_rw_addr_in_dout; + end + else begin + fifo_rw_addr_dout_1d <= fifo_rw_addr_dout_1d; + end + end + end + + // Instantiate the module + ddr3_rw_in_ctrl ddr3_rw_in_ctrl_inst( + .ui_clk_i (ui_clk_i), + .ui_rst_i (ui_rst_i), + .app_rdy_i (app_rdy), + .fifo_rw_in_empty_i (fifo_rw_in_empty), + .fifo_rw_in_re_o (fifo_rw_in_re), + .app_en_1d_o (app_en_1d) + ); + + // Instantiate the module + fifo_rw_cmd fifo_rw_cmd_inst ( + .wr_clk (sys_clk_i), + .rd_clk (ui_clk_i), + .rst (sys_rst_i), + .din (fifo_rw_cmd_din), + .wr_en (fifo_rw_cmd_we), + .full (fifo_rw_cmd_full), + .dout (fifo_rw_cmd_dout), + .rd_en (fifo_rw_cmd_re), + .empty (fifo_rw_cmd_empty) + ); + + // Instantiate the module + fifo_rw_addr fifo_rw_rw_addr_in_inst ( + .wr_clk (sys_clk_i), + .rd_clk (ui_clk_i), + .rst (sys_rst_i), + .din (fifo_rw_addr_in_din), + .wr_en (fifo_rw_addr_in_we), + .full (fifo_rw_addr_in_full), + .dout (fifo_rw_addr_in_dout), + .rd_en (fifo_rw_addr_in_re), + .empty (fifo_rw_addr_in_empty), + .valid () + ); + + + // Instantiate the module + fifo_wr_mask_data fifo_wr_mask_data_inst ( + .wr_clk (sys_clk_i), + .rd_clk (ui_clk_i), + .rst (sys_rst_i), + .din (fifo_wr_mask_data_din), + .wr_en (fifo_wr_mask_data_we), + .full (fifo_wr_mask_data_full), + .dout (fifo_wr_mask_data_dout), + .rd_en (fifo_wr_mask_data_re), + .empty (fifo_wr_mask_data_empty) + ); + + // Instantiate the module + fifo_rd_data fifo_rd_data_inst ( + .wr_clk (ui_clk_i), + .rd_clk (sys_clk_i), + .rst (ui_rst_i), + .din (fifo_rd_data_din), + .wr_en (fifo_rd_data_we), + .full (fifo_rd_data_full), + .dout (fifo_rd_data_dout), + .rd_en (fifo_rd_data_re), + .empty (fifo_rd_data_empty), + .valid (fifo_rd_data_valid) + ); + + fifo_rw_addr fifo_rw_rw_addr_out_inst( + .wr_clk (ui_clk_i), + .rd_clk (sys_clk_i), + .rst (ui_rst_i), + .din (fifo_rw_addr_out_din), + .wr_en (fifo_rw_addr_out_we), + .full (fifo_rw_addr_out_full), + .dout (fifo_rw_addr_out_dout), + .rd_en (fifo_rw_addr_out_re), + .empty (fifo_rw_addr_out_empty), + .valid (fifo_rw_addr_out_valid) + ); + + // Instantiate the module + fifo_rd_info fifo_rd_info_inst ( + .wr_clk (sys_clk_i), + .rst (sys_rst_i), + .din (fifo_rd_info_din), + .wr_en (fifo_rd_info_we), + .full (fifo_rd_info_full), + .dout (fifo_rd_info_dout), + .rd_en (fifo_rd_info_re), + .empty (fifo_rd_info_empty), + .valid (fifo_rd_info_valid) + ); +endmodule diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_rd_ctrl.v b/ddr3_general_design.srcs/sources_1/new/ddr3_rw_out_ctrl.v similarity index 81% rename from ddr3_general_design.srcs/sources_1/new/ddr3_rd_ctrl.v rename to ddr3_general_design.srcs/sources_1/new/ddr3_rw_out_ctrl.v index 78b5aaf..025e067 100644 --- a/ddr3_general_design.srcs/sources_1/new/ddr3_rd_ctrl.v +++ b/ddr3_general_design.srcs/sources_1/new/ddr3_rw_out_ctrl.v @@ -3,9 +3,9 @@ // Company: // Engineer: // -// Create Date: 2025/01/06 16:25:28 +// Create Date: 2025/01/13 18:31:58 // Design Name: -// Module Name: ddr3_rd_ctrl +// Module Name: ddr3_rw_out_ctrl // Project Name: // Target Devices: // Tool Versions: @@ -20,7 +20,7 @@ ////////////////////////////////////////////////////////////////////////////////// -module ddr3_rd_ctrl( +module ddr3_rw_out_ctrl( ); endmodule diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_ctrl_top.v b/ddr3_general_design.srcs/sources_1/new/ddr3_top.v similarity index 85% rename from ddr3_general_design.srcs/sources_1/new/ddr3_ctrl_top.v rename to ddr3_general_design.srcs/sources_1/new/ddr3_top.v index d0e8bcc..30bace6 100644 --- a/ddr3_general_design.srcs/sources_1/new/ddr3_ctrl_top.v +++ b/ddr3_general_design.srcs/sources_1/new/ddr3_top.v @@ -3,9 +3,9 @@ // Company: // Engineer: // -// Create Date: 2025/01/06 13:54:40 +// Create Date: 2025/01/13 18:25:16 // Design Name: -// Module Name: ddr3_ctrl_top +// Module Name: ddr3_top // Project Name: // Target Devices: // Tool Versions: @@ -19,8 +19,7 @@ // ////////////////////////////////////////////////////////////////////////////////// - -module ddr3_ctrl_top( +module ddr3_top( // Clock and reset signals input sys_clk_i, // 200MHz input sys_rst_i, // Active high @@ -30,29 +29,31 @@ module ddr3_ctrl_top( output init_calib_complete_1_o, // same as above // User interface signals - input [ 1:0] ddr3_0_rw_req_i, // 01: Write, 10: Read, 00 or 11: Idle - input [ 34:0] ddr3_0_rw_info_i, // Info in (1 Ctrl Signal + 5 Scr ID + 29 Address) - input [ 63:0] ddr3_0_wr_mask_i, // Mask in - input [511:0] ddr3_0_wr_data_i, // Data in - output ddr3_0_rw_ack_o, // Read/Write acknowledge - output ddr3_0_rw_full_o, // Write FIFO full when up to 32 + input ddr3_0_rw_en_i, + input [ 2:0] ddr3_0_rw_cmd_i, + input [ 28:0] ddr3_0_rw_addr_i, + input [ 63:0] ddr3_0_wr_mask_i, + input [511:0] ddr3_0_wr_data_i, + input [ 34:0] ddr3_0_rw_info_i, + output ddr3_0_rw_full_o, - output [ 28:0] ddr3_0_rd_info_o, // Info out - output [511:0] ddr3_0_rd_data_o, // Data out - output ddr3_0_rd_valid_o, // Read data & addr & id valid - output ddr3_0_rd_empty_o, // Read FIFO empty + output [511:0] ddr3_0_rd_data_o, + output [ 34:0] ddr3_0_rd_info_o, + output ddr3_0_rd_valid_o, + output ddr3_0_rd_empty_o, - input [ 1:0] ddr3_1_rw_req_i, // 01: Write, 10: Read, 00 or 11: Idle - input [ 34:0] ddr3_1_rw_info_i, // Info in - input [ 63:0] ddr3_1_wr_mask_i, // Mask in - input [511:0] ddr3_1_wr_data_i, // Data in - output ddr3_1_rw_ack_o, // Read/Write acknowledge - output ddr3_1_rw_full_o, // Write FIFO full when up to 32 + input ddr3_1_rw_en_i, + input [ 2:0] ddr3_1_rw_cmd_i, + input [ 28:0] ddr3_1_rw_addr_i, + input [ 63:0] ddr3_1_wr_mask_i, + input [511:0] ddr3_1_wr_data_i, + input [ 34:0] ddr3_1_rw_info_i, + output ddr3_1_rw_full_o, - output [ 98:0] ddr3_1_rd_info_o, // Info out - output [511:0] ddr3_1_rd_data_o, // Data out - output ddr3_1_rd_valid_o, // Read data & info valid - output ddr3_1_rd_empty_o, // Read FIFO empty + output [511:0] ddr3_1_rd_data_o, + output [ 34:0] ddr3_1_rd_info_o, + output ddr3_1_rd_valid_o, + output ddr3_1_rd_empty_o, // DDR3 interface signals inout [ 63:0] ddr3_0_dq_io, @@ -142,6 +143,9 @@ module ddr3_ctrl_top( assign app_1_ref_req = 1'b0; assign app_1_zq_req = 1'b0; + // Instantiate the module + ddr3_rw_module ddr3_rw_module_0_inst(); + // Instantiate the DDR3 controller ddr3_ctrl_0 ddr3_ctrl_0_inst ( .sys_clk_i (sys_clk_i ), @@ -187,6 +191,9 @@ module ddr3_ctrl_top( .app_zq_ack (app_0_zq_ack ) ); + // Instantiate the module + ddr3_rw_module ddr3_rw_module_1_inst(); + // Instantiate the DDR3 controller ddr3_ctrl_1 ddr3_ctrl_1_inst ( .sys_clk_i (sys_clk_i ), diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_wr_ctrl.v b/ddr3_general_design.srcs/sources_1/new/ddr3_wr_ctrl.v deleted file mode 100644 index eaa4b39..0000000 --- a/ddr3_general_design.srcs/sources_1/new/ddr3_wr_ctrl.v +++ /dev/null @@ -1,81 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2025/01/06 16:25:28 -// Design Name: -// Module Name: ddr3_wr_ctrl -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module ddr3_wr_ctrl( - input sys_clk_i, - input sys_rst_i, - input ui_clk_i, - input ui_rst_i, - - input [1:0] rw_req_i, - output rw_full_o, - - input cmd_fifo_full_i, - input addr_i_fifo_full_i, - input wdata_fifo_full_i, - input cmd_fifo_empty_i, - input addr_i_fifo_empty_i, - input wdata_fifo_empty_i, - - output cmd_fifo_we_o, - output cmd_fifo_re_o, - output addr_i_fifo_we_o, - output addr_i_fifo_re_o, - output wdata_fifo_we_o, - output wdata_fifo_re_o -); - - // Instantiate the module - ddr3_wr_fifo_wr_fsm ddr3_wr_fifo_wr_fsm_inst ( - .sys_clk_i (sys_clk_i), - .sys_rst_i (sys_rst_i), - .ui_clk_i (ui_clk_i), - .ui_rst_i (ui_rst_i), - - .rw_req_i (rw_req_i), - .rw_full_o (rw_full_o), - - .cmd_fifo_full_i (cmd_fifo_full_i), - .addr_i_fifo_full_i (addr_i_fifo_full_i), - .wdata_fif_full_i (wdata_fifo_full_i), - - .cmd_fifo_we_o (cmd_fifo_we_o), - .addr_i_fifo_we_o (addr_i_fifo_we_o), - .wdata_fifo_we_o (wdata_fifo_we_o) - ); - - // Instantiate the module - ddr3_wr_fifo_rd_fsm ddr3_wr_fifo_rd_fsm_inst ( - .sys_clk_i (sys_clk_i), - .sys_rst_i (sys_rst_i), - .ui_clk_i (ui_clk_i), - .ui_rst_i (ui_rst_i), - - .cmd_fifo_empty (cmd_fifo_empty_i), - .addr_i_fifo_empty (addr_i_fifo_empty_i), - .wdata_fifo_empty (wdata_fifo_empty_i), - - .cmd_fifo_re_o (cmd_fifo_re_o), - .addr_i_fifo_re_o (addr_i_fifo_re_o), - .wdata_fifo_re_o (wdata_fifo_re_o) - ); -endmodule diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_wr_fifo_rd_fsm.v b/ddr3_general_design.srcs/sources_1/new/ddr3_wr_fifo_rd_fsm.v deleted file mode 100644 index c22531d..0000000 --- a/ddr3_general_design.srcs/sources_1/new/ddr3_wr_fifo_rd_fsm.v +++ /dev/null @@ -1,26 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2025/01/06 16:58:22 -// Design Name: -// Module Name: ddr3_wr_fifo_rd_fsm -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module ddr3_wr_fifo_rd_fsm( - - ); -endmodule diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_wr_fifo_wr_fsm.v b/ddr3_general_design.srcs/sources_1/new/ddr3_wr_fifo_wr_fsm.v deleted file mode 100644 index 6b900de..0000000 --- a/ddr3_general_design.srcs/sources_1/new/ddr3_wr_fifo_wr_fsm.v +++ /dev/null @@ -1,92 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2025/01/06 16:58:22 -// Design Name: -// Module Name: ddr3_wr_fifo_wr_fsm -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module ddr3_wr_fifo_wr_fsm( - input sys_clk_i, - input sys_rst_i, - input ui_clk_i, - input ui_rst_i, - - input [1:0] rw_req_i, - output rw_full_o, - - input cmd_fifo_full_i, - input addr_i_fifo_full_i, - input wdata_fifo_full_i, - - output [1:0] cmd_fifo_din_sel_o, - - output cmd_fifo_we_o, - output addr_i_fifo_we_o, - output wdata_fifo_we_o - ); - - localparam [1:0] - S_IDLE = 2'b00, - S_FIFO_WRITE = 2'b01, - S_FIFO_WAIT = 2'b10; - - - reg [1:0] c_state; - reg [1:0] n_state; - - always @(posedge sys_clk_i or negedge sys_rst_i) begin - if (sys_rst_i) begin - c_state <= S_IDLE; - end - else begin - c_state <= n_state; - end - end - - always @(*) begin - case (c_state) - S_IDLE: begin - if(rw_req_i == 2'b10 || rw_req_i == 2'b01) begin - n_state = S_FIFO_WRITE; - end - else begin - n_state = S_IDLE; - end - end - S_FIFO_WRITE: begin - if (cmd_fifo_full_i || addr_i_fifo_full_i || wdata_fifo_full_i) begin - n_state = S_FIFO_WAIT; - end - else begin - n_state = S_FIFO_WRITE; - end - end - S_FIFO_WAIT: begin - if (!cmd_fifo_full_i && !addr_i_fifo_full_i && !wdata_fifo_full_i) begin - n_state = S_FIFO_WRITE; - end - else begin - n_state = S_FIFO_WAIT; - end - end - default: begin - n_state = S_IDLE; - end - endcase; - end -endmodule diff --git a/ddr3_general_design.xpr b/ddr3_general_design.xpr index 5c4e16a..cb24d54 100644 --- a/ddr3_general_design.xpr +++ b/ddr3_general_design.xpr @@ -3,7 +3,7 @@ - +