SET_FLAG MODE BATCH
SET_FLAG STANDALONE_MODE TRUE
SET_PREFERENCE ipi_mode yes
SET_PREFERENCE is_ip_locked false
SET_PREFERENCE devicefamily kintex7
SET_PREFERENCE device xc7k325t
SET_PREFERENCE speedgrade -2
SET_PREFERENCE package ffg900
SET_PREFERENCE verilogsim true
SET_PREFERENCE vhdlsim false
SET_PREFERENCE designentry Verilog
SET_PREFERENCE outputdirectory d:/Project/Vivado/AX7325/ddr3_general_design/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/_tmp/
SET_PREFERENCE subworkingdirectory d:/Project/Vivado/AX7325/ddr3_general_design/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/_tmp/
SET_PREFERENCE flowvendor Other
SET_PREFERENCE tool vivado
SET_PARAMETER component_name pcie_ddr_mig_7series_0_0
SET_PREFERENCE compnamestatus 1
SET_PARAMETER component_name pcie_ddr_mig_7series_0_0
SET_PARAMETER xml_input_file D:/Project/Vivado/AX7325/ddr3_general_design/ddr_general_design.srcs/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/mig_b.prj
SET_PARAMETER data_dir_path c:/Xilinx/Vivado/2019.2/data/ip/xilinx/mig_7series_v4_2
SET_CORE_NAME Memory Interface Generator (MIG 7 Series)
SET_CORE_VERSION 4.2
SET_CORE_VLNV xilinx.com:ip:mig_7series:4.2
SET_CORE_PATH c:/Xilinx/Vivado/2019.2/data/ip/xilinx/mig_7series_v4_2
SET_CORE_DATASHEET c:/Xilinx/Vivado/2019.2/data/ip/xilinx/mig_7series_v4_2/data/docs/ds176_7series_MIS.pdf
