`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/03/19 10:26:57
// Design Name: 
// Module Name: fifo_axi_ctrl
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module fifo_axi_ctrl(
    input           clk                  ,
    input           rst                  , 

    input  [1:0]    rw_req               ,
    input  [32:0]   rw_addr              ,
    output          rw_fifo_buzy         ,
    input  [4:0]    rd_length            ,
    input  [511:0]  wr_data              ,
    input  [63:0]   wr_mask              ,
    input  [4:0]    rw_where             ,
    output          rw_in_fifo_ack       ,
    output [4:0]    rw_in_fifo_ack_2where,
    output [511:0]  rd_data              ,
    output          rd_valid             ,
    output [4:0]    rd_valid_2where      ,

    output          wr_start     ,
    output [31:0]   wr_adrs      ,
    output [9:0]    wr_len       ,
    input           wr_ready     ,
    input           wr_fifo_re   ,
    output [63:0]   wr_fifo_data ,
    input           wr_done      ,

    output          rd_start    ,
    output [32:0]   rd_adrs     ,
    output [9:0]    rd_len      ,
    input           rd_ready    ,
    input           rd_fifo_we  ,
    input [63:0]    rd_fifo_data,
    input           rd_done      
    );



    fifo2axi_convert fifo2axi_convert_inst(
        .clk                    (clk),         
        .rst                    (rst),         

        .rw_req                 (),
        .rw_addr                (),
        .rd_length              (),
        .wr_data                (),
        .wr_mask                (),
        .rw_where               (),
        .rw_in_fifo_ack         (),
        .rw_in_fifo_ack_2where  (),
        .rw_fifo_buzy           (),

        .wr_start               (),
        .wr_adrs                (),
        .wr_len                 (),
        .wr_ready               (),
        .wr_fifo_re             (),
        .wr_fifo_data           (),
        .wr_done                (),

        .rd_start               (),
        .rd_adrs                (),
        .rd_len                 (),
        .rd_ready               (),
        .rd_fifo_we             (),
        .rd_fifo_data           (),
        .rd_done                () 
    );

    axi2fifo_convert axi2fifo_convert_inst(

    );


    fifo_ddr_addr fifo_ddr_waddr_inst(
        .clk            (clk),
        .srst           (rst),
        .full           (fifo_ddr_waddr_full),
        .din            (fifo_ddr_waddr_din),
        .wr_en          (fifo_ddr_waddr_we),
        .empty          (fifo_ddr_waddr_empty),
        .dout           (fifo_ddr_waddr_dout),
        .rd_en          (fifo_ddr_waddr_re),
        .wr_ack         (fifo_ddr_waddr_wack),
        .valid          (fifo_ddr_waddr_rv)
    );

    fifo_ddr_data fifo_ddr_wdata_inst(
        .clk            (clk),
        .srst           (rst),
        .full           (fifo_ddr_wdata_full),
        .din            (fifo_ddr_wdata_din),
        .wr_en          (fifo_ddr_wdata_we),
        .empty          (fifo_ddr_wdata_empty),
        .dout           (fifo_ddr_wdata_dout),
        .rd_en          (fifo_ddr_wdata_re),
        .wr_ack         (fifo_ddr_wdata_wack),
        .valid          (fifo_ddr_wdata_rv)
    );

    fifo_ddr_addr fifo_ddr_raddr_inst(
        .clk            (clk),
        .srst           (rst),
        .full           (fifo_ddr_raddr_full),
        .din            (fifo_ddr_raddr_din),
        .wr_en          (fifo_ddr_raddr_we),
        .empty          (fifo_ddr_raddr_empty),
        .dout           (fifo_ddr_raddr_dout),
        .rd_en          (fifo_ddr_raddr_re),
        .wr_ack         (fifo_ddr_raddr_wack),
        .valid          (fifo_ddr_raddr_rv)
    );

    fifo_ddr_data fifo_ddr_rdata_inst(
        .clk            (clk),
        .srst           (srst),
        .full           (fifo_ddr_rdata_full),
        .din            (fifo_ddr_rdata_din),
        .wr_en          (fifo_ddr_rdata_we),
        .empty          (fifo_ddr_rdata_empty),
        .dout           (fifo_ddr_rdata_dout),
        .rd_en          (fifo_ddr_rdata_re),
        .wr_ack         (fifo_ddr_rdata_wack),
        .valid          (fifo_ddr_rdata_rv)
    );


    fifo_ddr_info fifo_ddr_info_inst(
        .clk            (clk),
        .srst           (rst),
        .full           (fifo_ddr_info_full),
        .din            (fifo_ddr_info_din),
        .wr_en          (fifo_ddr_info_we),
        .empty          (fifo_ddr_info_empty),
        .dout           (fifo_ddr_info_dout),
        .rd_en          (fifo_ddr_info_re),
        .wr_ack         (fifo_ddr_info_wack),
        .valid          (fifo_ddr_info_rv)
    );
endmodule
