`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/03/18 13:49:10
// Design Name: 
// Module Name: ddr_ctrl
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module ddr_ctrl_top(
    // Inouts
   inout [63:0]                         ddr3_dq,
   inout [7:0]                          ddr3_dqs_n,
   inout [7:0]                          ddr3_dqs_p,
   // Outputs
   output [15:0]                        ddr3_addr,
   output [2:0]                         ddr3_ba,
   output                               ddr3_cas_n,
   output                               ddr3_ras_n,
   output                               ddr3_we_n,
   output                               ddr3_reset_n,
   output [1:0]                         ddr3_ck_p,
   output [1:0]                         ddr3_ck_n,
   output [1:0]                         ddr3_cke,
   output [1:0]                         ddr3_cs_n,
   output [7:0]                         ddr3_dm,
   output [1:0]                         ddr3_odt,
   // Inputs
   input                                sys_clk_i,
   output                               tg_compare_error,
   output                               init_calib_complete,
   input                                sys_rst
    );

    
   //***************************************************************************
   // AXI4 Shim parameters
   //***************************************************************************
    localparam C_S_AXI_ID_WIDTH              = 4;
                                               // Width of all master and slave ID signals.
                                               // # = >= 1.
    localparam C_S_AXI_ADDR_WIDTH            = 33;
                                               // Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and
                                               // M_AXI_ARADDR for all SI/MI slots.
                                               // # = 32.
    localparam C_S_AXI_DATA_WIDTH            = 512;
                                               // Width of WDATA and RDATA on SI slot.
                                               // Must be <= APP_DATA_WIDTH.
                                               // # = 32, 64, 128, 256.
    localparam C_S_AXI_SUPPORTS_NARROW_BURST = 0;
                                               // Indicates whether to instatiate upsizer
                                               // Range: 0, 1

    



// Output declaration of module ddr_axi_rd
       wire [3:0]                        m_axi_arid;
       wire [32:0]                       m_axi_araddr;
       wire [7:0]                        m_axi_arlen;
       wire [2:0]                        m_axi_arsize;
       wire [1:0]                        m_axi_arburst;
       wire [0:0]                        m_axi_arlock;
       wire [3:0]                        m_axi_arcache;
       wire [2:0]                        m_axi_arprot;
       wire [3:0]                        m_axi_arqos;
       wire                              m_axi_arvalid;
       wire                              m_axi_rready;
       wire                              rd_ready;
       wire                              rd_fifo_we;
       wire [511:0]                      rd_fifo_data;
       wire                              rd_done;

// Output declaration of module ddr_axi_wr
       wire [3:0]                        m_axi_awid;
       wire [32:0]                       m_axi_awaddr;
       wire [7:0]                        m_axi_awlen;
       wire [2:0]                        m_axi_awsize;
       wire [1:0]                        m_axi_awburst;
       wire                              m_axi_awlock;
       wire [3:0]                        m_axi_awcache;
       wire [2:0]                        m_axi_awprot;
       wire [3:0]                        m_axi_awqos;
       wire                              m_axi_awvalid;
       wire [511:0]                      m_axi_wdata;
       wire [63:0]                       m_axi_wstrb;
       wire                              m_axi_wlast;
       wire                              m_axi_wvalid;
       wire                              m_axi_bready;
       wire                              wr_ready;
       wire                              wr_fifo_re;
       wire                              wr_done;

// Slave Interface Write Address Ports
       wire [C_S_AXI_ID_WIDTH-1:0]       s_axi_awid;
       wire [C_S_AXI_ADDR_WIDTH-1:0]     s_axi_awaddr;
       wire [7:0]                        s_axi_awlen;
       wire [2:0]                        s_axi_awsize;
       wire [1:0]                        s_axi_awburst;
       wire [0:0]                        s_axi_awlock;
       wire [3:0]                        s_axi_awcache;
       wire [2:0]                        s_axi_awprot;
       wire                              s_axi_awvalid;
       wire                              s_axi_awready;
// Slave Interface Write Data Ports
       wire [C_S_AXI_DATA_WIDTH-1:0]     s_axi_wdata;
       wire [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb;
       wire                              s_axi_wlast;
       wire                              s_axi_wvalid;
       wire                              s_axi_wready;
// Slave Interface Write Response Ports
       wire                              s_axi_bready;
       wire [C_S_AXI_ID_WIDTH-1:0]       s_axi_bid;
       wire [1:0]                        s_axi_bresp;
       wire                              s_axi_bvalid;
// Slave Interface Read Address Ports
       wire [C_S_AXI_ID_WIDTH-1:0]       s_axi_arid;
       wire [C_S_AXI_ADDR_WIDTH-1:0]     s_axi_araddr;
       wire [7:0]                        s_axi_arlen;
       wire [2:0]                        s_axi_arsize;
       wire [1:0]                        s_axi_arburst;
       wire [0:0]                        s_axi_arlock;
       wire [3:0]                        s_axi_arcache;
       wire [2:0]                        s_axi_arprot;
       wire                              s_axi_arvalid;
       wire                              s_axi_arready;
// Slave Interface Read Data Ports
       wire                              s_axi_rready;
       wire [C_S_AXI_ID_WIDTH-1:0]       s_axi_rid;
       wire [C_S_AXI_DATA_WIDTH-1:0]     s_axi_rdata;
       wire [1:0]                        s_axi_rresp;
       wire                              s_axi_rlast;
       wire                              s_axi_rvalid;

fifo_axi_ctrl fifo_axi_ctrl_inst(
       .rw_req                     (rw_req_i               ),
       .rw_addr                    (rw_addr_i              ),
       .rw_fifo_buzy               (rw_fifo_buzy_o         ),
       .rd_length                  (rd_length_i            ),         
       .wr_data                    (wr_data_i              ),
       .wr_mask                    (wr_mask_i              ),
       .rw_where                   (rw_where_i             ),
       .rw_in_fifo_ack             (rw_in_fifo_ack_o       ),
       .rw_in_fifo_ack_2where      (rw_in_fifo_ack_2where_o),
       .rd_data                    (rd_data_o              ),
       .rd_valid                   (rd_valid_o             ),
       .rd_valid_2where            (rd_valid_2where_o      )
);

ddr_axi_rd u_ddr_axi_rd(
       .aresetn        (aresetn       ),
       .aclk           (aclk          ),
       .m_axi_arid     (m_axi_arid    ),
       .m_axi_araddr   (m_axi_araddr  ),
       .m_axi_arlen    (m_axi_arlen   ),
       .m_axi_arsize   (m_axi_arsize  ),
       .m_axi_arburst  (m_axi_arburst ),
       .m_axi_arlock   (m_axi_arlock  ),
       .m_axi_arcache  (m_axi_arcache ),
       .m_axi_arprot   (m_axi_arprot  ),
       .m_axi_arqos    (m_axi_arqos   ),
       .m_axi_arvalid  (m_axi_arvalid ),
       .m_axi_arready  (m_axi_arready ),
       .m_axi_rid      (m_axi_rid     ),
       .m_axi_rdata    (m_axi_rdata   ),
       .m_axi_rresp    (m_axi_rresp   ),
       .m_axi_rlast    (m_axi_rlast   ),
       .m_axi_rvalid   (m_axi_rvalid  ),
       .m_axi_rready   (m_axi_rready  ),
       .rd_start       (rd_start      ),
       .rd_adrs        (rd_adrs       ),
       .rd_len         (rd_len        ),
       .rd_ready       (rd_ready      ),
       .rd_fifo_we     (rd_fifo_we    ),
       .rd_fifo_data   (rd_fifo_data  ),
       .rd_done        (rd_done       )
);

ddr_axi_wr u_ddr_axi_wr(
       .aresetn        (aresetn       ),
       .aclk           (aclk          ),
       .m_axi_awid     (m_axi_awid    ),
       .m_axi_awaddr   (m_axi_awaddr  ),
       .m_axi_awlen    (m_axi_awlen   ),
       .m_axi_awsize   (m_axi_awsize  ),
       .m_axi_awburst  (m_axi_awburst ),
       .m_axi_awlock   (m_axi_awlock  ),
       .m_axi_awcache  (m_axi_awcache ),
       .m_axi_awprot   (m_axi_awprot  ),
       .m_axi_awqos    (m_axi_awqos   ),
       .m_axi_awvalid  (m_axi_awvalid ),
       .m_axi_awready  (m_axi_awready ),
       .m_axi_wdata    (m_axi_wdata   ),
       .m_axi_wstrb    (m_axi_wstrb   ),
       .m_axi_wlast    (m_axi_wlast   ),
       .m_axi_wvalid   (m_axi_wvalid  ),
       .m_axi_wready   (m_axi_wready  ),
       .m_axi_bid      (m_axi_bid     ),
       .m_axi_bresp    (m_axi_bresp   ),
       .m_axi_bvalid   (m_axi_bvalid  ),
       .m_axi_bready   (m_axi_bready  ),
       .wr_start       (wr_start      ),
       .wr_adrs        (wr_adrs       ),
       .wr_len         (wr_len        ),
       .wr_ready       (wr_ready      ),
       .wr_fifo_re     (wr_fifo_re    ),
       .wr_fifo_data   (wr_fifo_data  ),
       .wr_done        (wr_done       )
);





ddr_ctrl ddr_ctrl_inst(
// Memory interface ports
       .ddr3_addr                      (ddr3_addr),
       .ddr3_ba                        (ddr3_ba),
       .ddr3_cas_n                     (ddr3_cas_n),
       .ddr3_ck_n                      (ddr3_ck_n),
       .ddr3_ck_p                      (ddr3_ck_p),
       .ddr3_cke                       (ddr3_cke),
       .ddr3_ras_n                     (ddr3_ras_n),
       .ddr3_we_n                      (ddr3_we_n),
       .ddr3_dq                        (ddr3_dq),
       .ddr3_dqs_n                     (ddr3_dqs_n),
       .ddr3_dqs_p                     (ddr3_dqs_p),

       .ddr3_reset_n                   (ddr3_reset_n),
       .init_calib_complete            (init_calib_complete),
       
       .ddr3_cs_n                      (ddr3_cs_n),
       .ddr3_dm                        (ddr3_dm),
       .ddr3_odt                       (ddr3_odt),

// Application interface ports
       .ui_clk                         (clk),
       .ui_clk_sync_rst                (rst),
       .mmcm_locked                    (mmcm_locked),
       .aresetn                        (aresetn),
       .app_sr_req                     (1'b0),
       .app_ref_req                    (1'b0),
       .app_zq_req                     (1'b0),
       .app_sr_active                  (app_sr_active),
       .app_ref_ack                    (app_ref_ack),
       .app_zq_ack                     (app_zq_ack),

// Slave Interface Write Address Ports
       .s_axi_awid                     (s_axi_awid),
       .s_axi_awaddr                   (s_axi_awaddr),
       .s_axi_awlen                    (s_axi_awlen),
       .s_axi_awsize                   (s_axi_awsize),
       .s_axi_awburst                  (s_axi_awburst),
       .s_axi_awlock                   (s_axi_awlock), 
       .s_axi_awcache                  (s_axi_awcache),
       .s_axi_awprot                   (s_axi_awprot), 
       .s_axi_awqos                    (4'h0),         
       .s_axi_awvalid                  (s_axi_awvalid),
       .s_axi_awready                  (s_axi_awready),

// Slave Interface Write Data Ports
       .s_axi_wdata                    (s_axi_wdata),
       .s_axi_wstrb                    (s_axi_wstrb),
       .s_axi_wlast                    (s_axi_wlast),
       .s_axi_wvalid                   (s_axi_wvalid),
       .s_axi_wready                   (s_axi_wready),

// Slave Interface Write Response Ports
       .s_axi_bid                      (s_axi_bid),
       .s_axi_bresp                    (s_axi_bresp),
       .s_axi_bvalid                   (s_axi_bvalid),
       .s_axi_bready                   (s_axi_bready),

// Slave Interface Read Address Ports
       .s_axi_arid                     (s_axi_arid),
       .s_axi_araddr                   (s_axi_araddr),
       .s_axi_arlen                    (s_axi_arlen),
       .s_axi_arsize                   (s_axi_arsize),
       .s_axi_arburst                  (s_axi_arburst),
       .s_axi_arlock                   (s_axi_arlock),  
       .s_axi_arcache                  (s_axi_arcache), 
       .s_axi_arprot                   (s_axi_arprot),  
       .s_axi_arqos                    (4'h0),          
       .s_axi_arvalid                  (s_axi_arvalid),
       .s_axi_arready                  (s_axi_arready),

// Slave Interface Read Data Ports
       .s_axi_rid                      (s_axi_rid),
       .s_axi_rdata                    (s_axi_rdata),
       .s_axi_rresp                    (s_axi_rresp),
       .s_axi_rlast                    (s_axi_rlast),
       .s_axi_rvalid                   (s_axi_rvalid),
       .s_axi_rready                   (s_axi_rready),

// System Clock Ports
       .sys_clk_i                       (sys_clk_i),
       .device_temp                     (device_temp),
       .sys_rst                         (sys_rst)

);

endmodule
