{
  "design": {
    "design_info": {
      "boundary_crc": "0x2D40D29FDD4A3A57",
      "device": "xc7k325tffg900-2",
      "name": "pcie_ddr",
      "synth_flow_mode": "Hierarchical",
      "tool_version": "2019.2",
      "validated": "true"
    },
    "design_tree": {
      "xdma_0": "",
      "mig_7series_0": "",
      "util_ds_buf_0": "",
      "clk_wiz_0": "",
      "axi_interconnect_0": {
        "xbar": "",
        "s00_couplers": {
          "auto_us": "",
          "auto_cc": ""
        },
        "s01_couplers": {
          "auto_us": "",
          "auto_cc": ""
        },
        "m00_couplers": {
          "auto_cc": ""
        },
        "s01_mmu": ""
      },
      "rst_clk_wiz_0_200M": "",
      "rst_mig_7series_0_100M": ""
    },
    "interface_ports": {
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        "mode": "Slave",
        "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0",
        "parameters": {
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            "value": "false",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "100000000",
            "value_src": "default"
          }
        }
      },
      "ddr": {
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        "vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
        "parameters": {
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            "value": "false",
            "value_src": "default"
          },
          "TIMEPERIOD_PS": {
            "value": "1250",
            "value_src": "default"
          },
          "MEMORY_TYPE": {
            "value": "COMPONENTS",
            "value_src": "default"
          },
          "DATA_WIDTH": {
            "value": "8",
            "value_src": "default"
          },
          "CS_ENABLED": {
            "value": "true",
            "value_src": "default"
          },
          "DATA_MASK_ENABLED": {
            "value": "true",
            "value_src": "default"
          },
          "SLOT": {
            "value": "Single",
            "value_src": "default"
          },
          "MEM_ADDR_MAP": {
            "value": "ROW_COLUMN_BANK",
            "value_src": "default"
          },
          "BURST_LENGTH": {
            "value": "8",
            "value_src": "default"
          },
          "AXI_ARBITRATION_SCHEME": {
            "value": "TDM",
            "value_src": "default"
          },
          "CAS_LATENCY": {
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            "value_src": "default"
          },
          "CAS_WRITE_LATENCY": {
            "value": "11",
            "value_src": "default"
          }
        }
      },
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        "vlnv": "xilinx.com:interface:pcie_7x_mgt_rtl:1.0"
      },
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        "mode": "Slave",
        "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
        "parameters": {
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            "value": "32"
          },
          "PROTOCOL": {
            "value": "AXI4"
          },
          "FREQ_HZ": {
            "value": "200000000"
          },
          "ID_WIDTH": {
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          },
          "ADDR_WIDTH": {
            "value": "32"
          },
          "AWUSER_WIDTH": {
            "value": "0"
          },
          "ARUSER_WIDTH": {
            "value": "0"
          },
          "WUSER_WIDTH": {
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          },
          "RUSER_WIDTH": {
            "value": "0"
          },
          "BUSER_WIDTH": {
            "value": "0"
          },
          "READ_WRITE_MODE": {
            "value": "READ_WRITE"
          },
          "HAS_BURST": {
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          },
          "HAS_LOCK": {
            "value": "1"
          },
          "HAS_PROT": {
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          },
          "HAS_CACHE": {
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          },
          "HAS_QOS": {
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          },
          "HAS_REGION": {
            "value": "0"
          },
          "HAS_WSTRB": {
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          },
          "HAS_BRESP": {
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          },
          "HAS_RRESP": {
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          },
          "SUPPORTS_NARROW_BURST": {
            "value": "1"
          },
          "NUM_READ_OUTSTANDING": {
            "value": "2"
          },
          "NUM_WRITE_OUTSTANDING": {
            "value": "2"
          },
          "MAX_BURST_LENGTH": {
            "value": "256"
          },
          "PHASE": {
            "value": "0.000",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "pcie_ddr_clk_in1_0",
            "value_src": "default"
          },
          "NUM_READ_THREADS": {
            "value": "1"
          },
          "NUM_WRITE_THREADS": {
            "value": "1"
          },
          "RUSER_BITS_PER_BYTE": {
            "value": "0"
          },
          "WUSER_BITS_PER_BYTE": {
            "value": "0"
          },
          "INSERT_VIP": {
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            "value_src": "default"
          }
        }
      }
    },
    "ports": {
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        "type": "clk",
        "direction": "I",
        "parameters": {
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            "value": "ddr_axi",
            "value_src": "default"
          },
          "ASSOCIATED_RESET": {
            "value": "sys_rstn",
            "value_src": "default"
          },
          "CLK_DOMAIN": {
            "value": "pcie_ddr_clk_in1_0",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "200000000"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.000",
            "value_src": "default"
          }
        }
      },
      "sys_rstn": {
        "type": "rst",
        "direction": "I",
        "parameters": {
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "POLARITY": {
            "value": "ACTIVE_LOW",
            "value_src": "default"
          }
        }
      },
      "sys_rst_n_0": {
        "type": "rst",
        "direction": "I",
        "parameters": {
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "POLARITY": {
            "value": "ACTIVE_LOW",
            "value_src": "default"
          }
        }
      },
      "init_calib_complete": {
        "direction": "O"
      },
      "pcie_user_lnk_up": {
        "direction": "O"
      },
      "pcie_msi_enable": {
        "direction": "O"
      },
      "pcie_usr_irq_req": {
        "direction": "I",
        "left": "0",
        "right": "0"
      }
    },
    "components": {
      "xdma_0": {
        "vlnv": "xilinx.com:ip:xdma:4.1",
        "xci_name": "pcie_ddr_xdma_0_0",
        "parameters": {
          "PF0_DEVICE_ID_mqdma": {
            "value": "9028"
          },
          "PF2_DEVICE_ID_mqdma": {
            "value": "9028"
          },
          "PF3_DEVICE_ID_mqdma": {
            "value": "9028"
          },
          "axi_data_width": {
            "value": "128_bit"
          },
          "axisten_freq": {
            "value": "250"
          },
          "mode_selection": {
            "value": "Advanced"
          },
          "pf0_class_code_base": {
            "value": "05"
          },
          "pf0_class_code_interface": {
            "value": "00"
          },
          "pf0_class_code_sub": {
            "value": "80"
          },
          "pf0_device_id": {
            "value": "7028"
          },
          "pf0_sub_class_interface_menu": {
            "value": "Generic_XT_compatible_serial_controller"
          },
          "pl_link_cap_max_link_speed": {
            "value": "5.0_GT/s"
          },
          "pl_link_cap_max_link_width": {
            "value": "X8"
          },
          "plltype": {
            "value": "QPLL1"
          },
          "xdma_rnum_chnl": {
            "value": "2"
          },
          "xdma_wnum_chnl": {
            "value": "2"
          }
        }
      },
      "mig_7series_0": {
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        "xci_name": "pcie_ddr_mig_7series_0_0",
        "parameters": {
          "BOARD_MIG_PARAM": {
            "value": "Custom"
          },
          "RESET_BOARD_INTERFACE": {
            "value": "Custom"
          },
          "XML_INPUT_FILE": {
            "value": "mig_b.prj"
          }
        }
      },
      "util_ds_buf_0": {
        "vlnv": "xilinx.com:ip:util_ds_buf:2.1",
        "xci_name": "pcie_ddr_util_ds_buf_0_0",
        "parameters": {
          "C_BUF_TYPE": {
            "value": "IBUFDSGTE"
          }
        }
      },
      "clk_wiz_0": {
        "vlnv": "xilinx.com:ip:clk_wiz:6.0",
        "xci_name": "pcie_ddr_clk_wiz_0_0",
        "parameters": {
          "CLKIN1_JITTER_PS": {
            "value": "50.0"
          },
          "CLKOUT1_JITTER": {
            "value": "98.146"
          },
          "CLKOUT1_PHASE_ERROR": {
            "value": "89.971"
          },
          "CLKOUT1_REQUESTED_OUT_FREQ": {
            "value": "200"
          },
          "MMCM_CLKFBOUT_MULT_F": {
            "value": "5.000"
          },
          "MMCM_CLKIN1_PERIOD": {
            "value": "5.000"
          },
          "MMCM_CLKIN2_PERIOD": {
            "value": "10.0"
          },
          "MMCM_CLKOUT0_DIVIDE_F": {
            "value": "5.000"
          },
          "PRIM_IN_FREQ": {
            "value": "200.000"
          },
          "RESET_PORT": {
            "value": "resetn"
          },
          "RESET_TYPE": {
            "value": "ACTIVE_LOW"
          }
        }
      },
      "axi_interconnect_0": {
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        "xci_name": "pcie_ddr_axi_interconnect_0_1",
        "parameters": {
          "NUM_MI": {
            "value": "1"
          },
          "NUM_SI": {
            "value": "2"
          }
        },
        "interface_ports": {
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            "mode": "Slave",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M00_AXI": {
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            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
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          "S01_AXI": {
            "mode": "Slave",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          }
        },
        "ports": {
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            "type": "clk",
            "direction": "I",
            "parameters": {
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                "value": "ARESETN"
              }
            }
          },
          "ARESETN": {
            "type": "rst",
            "direction": "I"
          },
          "S00_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "S00_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "S00_ARESETN"
              }
            }
          },
          "S00_ARESETN": {
            "type": "rst",
            "direction": "I"
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          "M00_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "M00_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "M00_ARESETN"
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          },
          "M00_ARESETN": {
            "type": "rst",
            "direction": "I"
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          "S01_ACLK": {
            "type": "clk",
            "direction": "I",
            "parameters": {
              "ASSOCIATED_BUSIF": {
                "value": "S01_AXI"
              },
              "ASSOCIATED_RESET": {
                "value": "S01_ARESETN"
              }
            }
          },
          "S01_ARESETN": {
            "type": "rst",
            "direction": "I"
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        },
        "components": {
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            "xci_name": "pcie_ddr_xbar_1",
            "parameters": {
              "NUM_MI": {
                "value": "1"
              },
              "NUM_SI": {
                "value": "2"
              },
              "STRATEGY": {
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              }
            }
          },
          "s00_couplers": {
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                "mode": "Master",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
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                "type": "clk",
                "direction": "I",
                "parameters": {
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                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
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              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
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              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
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                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
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                "xci_name": "pcie_ddr_auto_us_0",
                "parameters": {
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                    "value": "512"
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                  "SI_DATA_WIDTH": {
                    "value": "128"
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                }
              },
              "auto_cc": {
                "vlnv": "xilinx.com:ip:axi_clock_converter:2.1",
                "xci_name": "pcie_ddr_auto_cc_2"
              }
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                  "auto_us/S_AXI"
                ]
              },
              "auto_cc_to_s00_couplers": {
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                  "auto_cc/M_AXI"
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                  "auto_cc/S_AXI"
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                "ports": [
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                  "auto_us/s_axi_aclk",
                  "auto_cc/s_axi_aclk"
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                "ports": [
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                  "auto_us/s_axi_aresetn",
                  "auto_cc/s_axi_aresetn"
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                "ports": [
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                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
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                "mode": "Slave",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
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                "type": "clk",
                "direction": "I",
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                  "ASSOCIATED_RESET": {
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                "direction": "I"
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                  }
                }
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                "xci_name": "pcie_ddr_auto_cc_3"
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                  "auto_us/S_AXI"
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              "auto_cc_to_s01_couplers": {
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                  "auto_cc/m_axi_aclk"
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                "ports": [
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                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              },
              "S_AXI": {
                "mode": "Slave",
                "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
              }
            },
            "ports": {
              "M_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
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                    "value": "M_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "M_ARESETN"
                  }
                }
              },
              "M_ARESETN": {
                "type": "rst",
                "direction": "I"
              },
              "S_ACLK": {
                "type": "clk",
                "direction": "I",
                "parameters": {
                  "ASSOCIATED_BUSIF": {
                    "value": "S_AXI"
                  },
                  "ASSOCIATED_RESET": {
                    "value": "S_ARESETN"
                  }
                }
              },
              "S_ARESETN": {
                "type": "rst",
                "direction": "I"
              }
            },
            "components": {
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                "vlnv": "xilinx.com:ip:axi_clock_converter:2.1",
                "xci_name": "pcie_ddr_auto_cc_1"
              }
            },
            "interface_nets": {
              "auto_cc_to_m00_couplers": {
                "interface_ports": [
                  "M_AXI",
                  "auto_cc/M_AXI"
                ]
              },
              "m00_couplers_to_auto_cc": {
                "interface_ports": [
                  "S_AXI",
                  "auto_cc/S_AXI"
                ]
              }
            },
            "nets": {
              "M_ACLK_1": {
                "ports": [
                  "M_ACLK",
                  "auto_cc/m_axi_aclk"
                ]
              },
              "S_ACLK_1": {
                "ports": [
                  "S_ACLK",
                  "auto_cc/s_axi_aclk"
                ]
              },
              "M_ARESETN_1": {
                "ports": [
                  "M_ARESETN",
                  "auto_cc/m_axi_aresetn"
                ]
              },
              "S_ARESETN_1": {
                "ports": [
                  "S_ARESETN",
                  "auto_cc/s_axi_aresetn"
                ]
              }
            }
          },
          "s01_mmu": {
            "vlnv": "xilinx.com:ip:axi_mmu:2.1",
            "xci_name": "pcie_ddr_s01_mmu_1"
          }
        },
        "interface_nets": {
          "s01_couplers_to_xbar": {
            "interface_ports": [
              "s01_couplers/M_AXI",
              "xbar/S01_AXI"
            ]
          },
          "m00_couplers_to_axi_interconnect_0": {
            "interface_ports": [
              "M00_AXI",
              "m00_couplers/M_AXI"
            ]
          },
          "xbar_to_m00_couplers": {
            "interface_ports": [
              "xbar/M00_AXI",
              "m00_couplers/S_AXI"
            ]
          },
          "s01_mmu_M_AXI": {
            "interface_ports": [
              "s01_mmu/M_AXI",
              "s01_couplers/S_AXI"
            ]
          },
          "S01_AXI_1": {
            "interface_ports": [
              "S01_AXI",
              "s01_mmu/S_AXI"
            ]
          },
          "axi_interconnect_0_to_s00_couplers": {
            "interface_ports": [
              "S00_AXI",
              "s00_couplers/S_AXI"
            ]
          },
          "s00_couplers_to_xbar": {
            "interface_ports": [
              "s00_couplers/M_AXI",
              "xbar/S00_AXI"
            ]
          }
        },
        "nets": {
          "axi_interconnect_0_ACLK_net": {
            "ports": [
              "ACLK",
              "xbar/aclk",
              "s00_couplers/M_ACLK",
              "s01_couplers/M_ACLK",
              "m00_couplers/S_ACLK"
            ]
          },
          "axi_interconnect_0_ARESETN_net": {
            "ports": [
              "ARESETN",
              "xbar/aresetn",
              "s00_couplers/M_ARESETN",
              "s01_couplers/M_ARESETN",
              "m00_couplers/S_ARESETN"
            ]
          },
          "S00_ACLK_1": {
            "ports": [
              "S00_ACLK",
              "s00_couplers/S_ACLK"
            ]
          },
          "S00_ARESETN_1": {
            "ports": [
              "S00_ARESETN",
              "s00_couplers/S_ARESETN"
            ]
          },
          "S01_ACLK_1": {
            "ports": [
              "S01_ACLK",
              "s01_couplers/S_ACLK",
              "s01_mmu/aclk"
            ]
          },
          "S01_ARESETN_1": {
            "ports": [
              "S01_ARESETN",
              "s01_couplers/S_ARESETN",
              "s01_mmu/aresetn"
            ]
          },
          "M00_ACLK_1": {
            "ports": [
              "M00_ACLK",
              "m00_couplers/M_ACLK"
            ]
          },
          "M00_ARESETN_1": {
            "ports": [
              "M00_ARESETN",
              "m00_couplers/M_ARESETN"
            ]
          }
        }
      },
      "rst_clk_wiz_0_200M": {
        "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
        "xci_name": "pcie_ddr_rst_clk_wiz_0_200M_0"
      },
      "rst_mig_7series_0_100M": {
        "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
        "xci_name": "pcie_ddr_rst_mig_7series_0_100M_4"
      }
    },
    "interface_nets": {
      "mig_7series_0_DDR3": {
        "interface_ports": [
          "ddr",
          "mig_7series_0/DDR3"
        ]
      },
      "xdma_0_pcie_mgt": {
        "interface_ports": [
          "pcie_mgt",
          "xdma_0/pcie_mgt"
        ]
      },
      "CLK_IN_D_0_1": {
        "interface_ports": [
          "pcie_clk",
          "util_ds_buf_0/CLK_IN_D"
        ]
      },
      "S01_AXI_0_1": {
        "interface_ports": [
          "ddr_axi",
          "axi_interconnect_0/S01_AXI"
        ]
      },
      "xdma_0_M_AXI": {
        "interface_ports": [
          "xdma_0/M_AXI",
          "axi_interconnect_0/S00_AXI"
        ]
      },
      "axi_interconnect_0_M00_AXI": {
        "interface_ports": [
          "axi_interconnect_0/M00_AXI",
          "mig_7series_0/S_AXI"
        ]
      }
    },
    "nets": {
      "clk_in1_0_1": {
        "ports": [
          "sys_clk",
          "clk_wiz_0/clk_in1",
          "axi_interconnect_0/S01_ACLK"
        ]
      },
      "resetn_0_1": {
        "ports": [
          "sys_rstn",
          "clk_wiz_0/resetn",
          "rst_clk_wiz_0_200M/ext_reset_in",
          "axi_interconnect_0/S01_ARESETN"
        ]
      },
      "clk_wiz_0_clk_out1": {
        "ports": [
          "clk_wiz_0/clk_out1",
          "mig_7series_0/sys_clk_i",
          "axi_interconnect_0/ACLK",
          "rst_clk_wiz_0_200M/slowest_sync_clk"
        ]
      },
      "util_ds_buf_0_IBUF_OUT": {
        "ports": [
          "util_ds_buf_0/IBUF_OUT",
          "xdma_0/sys_clk"
        ]
      },
      "sys_rst_n_0_1": {
        "ports": [
          "sys_rst_n_0",
          "xdma_0/sys_rst_n"
        ]
      },
      "clk_wiz_0_locked": {
        "ports": [
          "clk_wiz_0/locked",
          "mig_7series_0/sys_rst",
          "rst_clk_wiz_0_200M/dcm_locked"
        ]
      },
      "mig_7series_0_init_calib_complete": {
        "ports": [
          "mig_7series_0/init_calib_complete",
          "init_calib_complete"
        ]
      },
      "xdma_0_user_lnk_up": {
        "ports": [
          "xdma_0/user_lnk_up",
          "pcie_user_lnk_up"
        ]
      },
      "xdma_0_msi_enable": {
        "ports": [
          "xdma_0/msi_enable",
          "pcie_msi_enable"
        ]
      },
      "usr_irq_req_0_1": {
        "ports": [
          "pcie_usr_irq_req",
          "xdma_0/usr_irq_req"
        ]
      },
      "rst_clk_wiz_0_200M_peripheral_aresetn": {
        "ports": [
          "rst_clk_wiz_0_200M/peripheral_aresetn",
          "axi_interconnect_0/ARESETN"
        ]
      },
      "xdma_0_axi_aclk": {
        "ports": [
          "xdma_0/axi_aclk",
          "axi_interconnect_0/S00_ACLK"
        ]
      },
      "xdma_0_axi_aresetn": {
        "ports": [
          "xdma_0/axi_aresetn",
          "axi_interconnect_0/S00_ARESETN"
        ]
      },
      "mig_7series_0_ui_clk": {
        "ports": [
          "mig_7series_0/ui_clk",
          "axi_interconnect_0/M00_ACLK",
          "rst_mig_7series_0_100M/slowest_sync_clk"
        ]
      },
      "mig_7series_0_mmcm_locked": {
        "ports": [
          "mig_7series_0/mmcm_locked",
          "rst_mig_7series_0_100M/dcm_locked"
        ]
      },
      "mig_7series_0_ui_clk_sync_rst": {
        "ports": [
          "mig_7series_0/ui_clk_sync_rst",
          "rst_mig_7series_0_100M/ext_reset_in"
        ]
      },
      "rst_mig_7series_0_100M_peripheral_aresetn": {
        "ports": [
          "rst_mig_7series_0_100M/peripheral_aresetn",
          "mig_7series_0/aresetn",
          "axi_interconnect_0/M00_ARESETN"
        ]
      }
    },
    "addressing": {
      "/": {
        "address_spaces": {
          "ddr_axi": {
            "range": "4G",
            "width": "32",
            "segments": {
              "SEG_mig_7series_0_memaddr": {
                "address_block": "/mig_7series_0/memmap/memaddr",
                "offset": "0x00000000",
                "range": "4G"
              }
            }
          }
        }
      },
      "/xdma_0": {
        "address_spaces": {
          "M_AXI": {
            "range": "16E",
            "width": "32",
            "segments": {
              "SEG_mig_7series_0_memaddr": {
                "address_block": "/mig_7series_0/memmap/memaddr",
                "offset": "0x0000000000000000",
                "range": "8G"
              }
            }
          }
        }
      }
    }
  }
}