`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/03/19 10:25:21
// Design Name: 
// Module Name: fifo2axi_convert
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module fifo2axi_convert(
    input clk,
    input rst,

    input [1:0] rw_req               ,
    input [32:0] rw_addr              ,
    input [4:0] rd_length            ,
    input [511:0] wr_data              ,
    input [63:0] wr_mask              ,
    input [4:0] rw_where             ,
    output  rw_in_fifo_ack       ,
    output [4:0] rw_in_fifo_ack_2where,
    output rw_fifo_buzy         ,

    output reg      wr_start     ,
    input           wr_ready     ,
    input           wr_fifo_re   ,
    input           wr_done      ,

    input           fifo_ddr_waddr_full,
    output reg      fifo_ddr_waddr_we,
    input           fifo_ddr_waddr_empty,
    output reg      fifo_ddr_waddr_re,
    input           fifo_ddr_waddr_wack,
    input           fifo_ddr_waddr_rv,

    output          rd_start    ,
    output [32:0]   rd_adrs     ,
    output [9:0]    rd_len      ,
    input           rd_ready    ,
    input           rd_fifo_we  ,
    input           rd_done                
    );

    localparam [1:0] 
        S_IDLE      = 2'd0,
        S_FIFO_RD   = 2'd1,
        S_WR_START  = 2'd2,
;

    reg [1:0] c_state;
    reg [1:0] n_state;

    always @(posedge clk or posedge rst) begin
        if(rst) begin
            c_state <= 0;
        end
        else begin
            c_state <= n_state;
        end
    end

    always @(*) begin
        wr_start            <= 1'b0;
        fifo_ddr_waddr_we   <= 1'b0;
        fifo_ddr_waddr_re   <= 1'b0;
        case(c_state)
            S_IDLE: begin
                casex({wr_ready, !fifo_ddr_waddr_empty})
                    2'b11: begin
                        n_state             <= S_FIFO_RD;
                        fifo_ddr_waddr_re   <= 1'b1;
                    end
                    default: begin
                        n_state = S_IDLE;
                    end
                endcase
            end
            S_FIFO_RD: begin
                n_state             <= S_WR_START;
                wr_start            <= 1'b1;
            end
        endcase
    end

endmodule
